Method of making semiconductor devices



July 11, 1967 G. R. BROUSSARD METHOD OF MAKING SEMICONDUCTOR DEVICES 2Sheets-Sheet 1 Original Filed Sept. 29, 1961 Fig. 2c

Fig. la

mm m F w Q m M m m F a 0 m GERALD R..BROU$SARD I NVEN TOR.

July 11, 1967 G. R. BROUSSARD 3,330,030

METHOD OF MAKING SEMICONDUCTOR DEVICES Original Filed Sept. 29, 1961 50Fig. 3a

5"/58) Fig. 3d

GERALD R. BROUSSARD INVENTOR.

2 Sheets-$heef United States Patent 3,330,030 METHOD OF MAKINGSEMICONDUCTOR DEVICES Gerald R. Broussard, Richardson, Tex., assiguor toTexas Instruments Incorporated, Dallas, Tex., a corporation of DelawareOriginal application Sept. 29, 1961, Ser. No. 141,708, now Patent No.3,197,681, dated July 27, 1965. Divided and this application May 4,1964, Ser. No. 369,341

6 Claims. (Cl. 29-589) This is a divisional application of copendingapplication Serial No. 141,708, filed September 29, 1961, now Patent No.3,197,681.

This invention relates to semiconductor devices and fabricationtechnique therefor. More specifically, this invention relates totransistors and switching devices in which at least three of theelectrodes are bonded to a single surface of the device.

Planar transistors are a relatively new concept in the semiconductorfield. The designation of a transistor as being of the planar type willbe distinguished from transistors of the mesa type as follows. As ageneral rule the base-collector junction area of a mesa type transistoris reduced by etching techniques after the basecollector junction isformed. In the fabrication of a planar type transistor, however, thebase-collector junction area is restricted during its formation, therebyremoving the necessity of subsequently reducing this area.

Planar transistors, usually of the NPN silicon variety, ordinarily havethe emitter and base contacts on the upper planar surface of the device,the collector contact being made to the bottom of the device by weldingor soldering the wafer to a metal header. The present invention providesa method by which not only the emitter and base contact but also thecollector contact can be made to a single side of the wafer. Anadvantage of having all three contacts of a transistor bonded on asingle side of the wafer is that the transistor can be easilyelectrically isolated from the metal header by mounting the wafer on aninsulator.

Pure gold, or antimony-doped gold, can be used to alloy the collector ofa NPN transistor to a metal header, thus forming an ohmic contact to thecollector region. It must be noted, however, that it is extremely hardto control the alloying depth of gold in silicon. Collector regions oftransistors are normally sufficiently thick so that no real problemarises when forming the collector contact by alloying the collector sideof the transistor wafer to a metal header with a gold preform. This isnot the case if the collector contact is to be made to the same surfaceof the transistor wafer as are the emitter and base contacts. As will beseen in the following discussion, gold cannot be used because of theuncontrollability of the alloying depth in silicon.

The use of aluminum as a metal contacting member is highly desirable inview of its electrical, thermal and physical characteristics. Aluminumcan be ohmically alloyed to either p-type or very highly doped n-typesilicon, although a strong rectifying junction will be produced ifaluminum is alloyed to the lightly doped ntype collector region of anNPN silicon transistor. The present invention provides a method,however, whereby aluminum can be used as the emitter, base and collectorcontacts by alloying to the three respective regions without creatingrectifying junctions. During the emitter diffusion in the fabrication ofthe transistor, an additional diffusion is made into the upper side ofthe collector region so that aluminum may consequently be ohmicallyalloyed thereto.

A silicon dioxide surface layer is often used to protect any normallyexposed active junctions from harmful impurities. Although thermallygrown silicon dioxide lay- "ice ers are very useful for junctionprotection, they are not completely effective in preventingcontamination. For example, the surface of a p-type conductivity regioncan be inverted to n-type conductivity by contaminants. Thus, if thesurface of a p-type conductivity base region is inverted to n-typeconductivity, an electrical short occurs as a result of the continuousn-type conductivity path from the n-type conductivity emitter region tothe n-type conductivity collector region. This is a quite differentproblem than that encountered when the rectifying junction becomescontaminated. In fact the rectifying junctions of the transistors can beeffectively protected from contamination by use of surface layers ofsilicon dioxide, and yet, some degree of electrical shorting is stillprevalent as a result of the inversion of the surfaces of the activeregions of the transistor.

Some degree of protection against inversion layers is afforded bymethods used in fabricating planar transistors of the prior art. Forexample, when aluminum, as an electrical contact member, is alloyed tothe p-type conductivity base region of a planar NPN silicon transistor,the aluminum increases the p-type impurity level in the vicinity of thesilicon-aluminum alloy to such a degree that inversion is practicallynon-existent. That is, the impurity level in the vicinity of thealuminum contact is increased from about 10 impurities per cubiccentimeter (about the normal doping level of the base region of an NPNsilicon transistor) to about 10 impurities per cubic centimeter. Thus, abarrier is provided to prevent electrical conduction across the surfaceof the base region that ordinarily would exist as a result of theremainder of the base region surface inverting from one typeconductivity to the opposite type conductivity.

Although transistors are thus protected against junction contaminationand complete inversion of the base region surface, inversion of thecollector region surface is still possible. An electrical short canoccur from the base region to the ohmic contact on the collector region,thus causing the collector region to be electrically shunted orcompletely shorted out. The present invention, while providing a planartransistor whereby electrical contacts can be made to the emitter, baseand collector regions on one surface of the transistor wafer, alsoprovides a transistor with an effective barrier in the collector regionfor preventing electrical shorting across the surface of the collectorregion.

It is a principal object of the present invention to provide atransistor having all of its electrical contacts positioned insubstantially one plane. Another object of the present invention is toprovide a novel semiconductor switching device having at least threeelectrical contacts positioned in substantially one plane. A furtherobject is to provide a planar transistor with protection againstinversion layers on the surface of the collector region. An additionalobject is to provide a novel transistor that may easily be mounted on ametal header, and yet, be electrically isolated therefrom. Still anotherobject is to provide an NPN planar transistor utilizing aluminum as acontact member to the collector region.

Other objects and advantages of the present invention will becomeapparent from the following detailed description when taken inconnection with the accompanying drawings, in which;

FIGURES la-le are pictorial views, in section, of a semiconductor waferduring the fabrication steps of a preferred embodiment of the presentinvention.

FIGURES 2a-2d are pictorial views, in section, of a semiconductor waferin various stages 0 fthe fabrication of a PNPN switch according to thisinvention; and

FIGURES 3a3d are pictorial views, in section, of a semiconductor waferin various stages in the fabrication asaaoao 3 of a NPN mesa transistoraccording to the present invention.

Referring now to FIGURES 1a through 1e, a detailed description will begiven for the process of fabricating a novel transistor in accordancewith this invention. A semiconductor wafer 10, preferably beingsiliconof N-type conductivity and of resistivity of approximately '10 ohmcm. isutilized as a starting material. A silicon dioxide layer 11 is formed onone surface of the semiconductor wafer by any well known technique suchas passing steam over the wafer '10 at a temperature of approximately1100 C. After the oxide layer 11 has been formed, photoresist techniquesare used to selectively mask a portion of the layer, a circular portionof the oxide layer 11 in the center being left unmasked. Hydrofluoricacid or some mixture containing hydrofluoric acid is used to remove theunmasked portions of the oxide, thus cutting away a circular portion 12of the oxide and exposing a surface portion 13 of the semiconductorwafer 10 as shown in FIGURE 1b. Subsequently, a P-type determiningimpurity is diffused into the unmasked portion 13 of the semiconductorwafer 10 to create a P-type region 14. For example, boric acid can bepainted on the surface of the wafer and diffused therein. The diffusionis carried out in an open tube furnace at approximately 1000 C. for aperiod of from about 20 to 30 minutes. Under these conditions, the borondiffuses into the wafer 10 to form a P-type region 14 to a depth ofapproximately 0.16 mil. During the diffusion of the boron into thesemiconductor wafer 10, wet nitrogen is passed over the surface of thewafer, the water in the nitrogen becoming steam and forming an oxidelayer 15 overrthe unmasked portion. Alternatively, the remainder of theoxide coating 11 could be removed and an oxide layer 15 formed over theentire wafer ina subsequent operation. In either case, the top surfaceof the wafer is covered by oxide. A sectional view of the wafer afterthe boron diffusion and reoxidation by the wet nitrogen is shown inFIGURE 10. That is, a P-type conductivity base region 14 is formed witha continuous film of silicon dioxide 15 covering the surface of thewafer 10.

Again photoresist techniques are used to selectively mask the silicondioxide layer 15. The unmaskedoxide layer covering a circular portion 16of the base region 14 as shown in FIGURE 14 is etched away. In addition,a ring of oxide on the outer perimeter of the wafer surface is removedto expose an outer edge 17 of the top surface of the wafer *10. As shownin FIGURE 1d, the remainder of the oxide layer 15 covers the junctionbetween the P-type region 14 and the wafer 10. e

Phosphorus is diffused into the wafer surface portions 15 and 17 wherethe silicon dioxide is removed, this form- .ing a diffused emitterregion 18 and a very highly doped N-type region 19 as shown in FIGURE1d. For example, it has been found that heating the silicon wafer 10toapproximately 1200" C. and passing phosphorus pentoxide over the surfacethereof will produce a satisfactory diffusion of phosphorus into thewafer in the regions 18 and '19. In this instance, wet nitrogen can beused as a carrier gasfor the phosphorus pentoxide, the heated siliconwafer 10 causing the phosphorus pentoxide'to decompose and depositphosporus on the surface thereof. The diffusion is carried out over atime of from about 30 to 60 minutes, thus producing a depth ofpenetration of approximately 0.11 mil.

During the diffusion of the phosphorus into the wafer 10, silicondioxide is formed on the surface of the wafer. This is caused by the Wetnitrogen flowing over the heated silicon wafer 10. FIGURE 1d, asectional view of the semiconductor wafer 10 after the phosphorusdiffusion, shows the emitter region 18 formed by the phosphorusdiffusion, the base region 14 formed by the previous boron diffusion,and the highly doped N-type conductivity region 19 formed by thephosphorus diffusion. During the phosphorus diffusion, or subsequentlyif convenient, a

continuous silicon dioxide layer 20 as shown in FIGURE 1e is formed overthe entire top surface of the semiconductor wafer 10. If the oxide layer15 has not been removed, it will of course form an integral part of theoxide layer 20.

The diffusion of the boron into the semiconductor wafer 10has the effectof producing in the wafer a P-type'base region 14 having a doping levelof about 10 P-type impurities per cubic centimeter whereas the originalN- type conductivity wafer impurity level is about 10 to 10 N-typeimpurities per cubic centimeter. The diffusion of the phosphorus intothe P-type conductivity base region 14 has theeffect of creating anN-type conductivity emitter region 18 therein. Because of the very highsolid solubility of phosphorus silicon avery high phosphorus surfaceconcentration is attained during the emitter diifusion. The resultingemitter region 18 is highly doped and has in the order of 10 (orgreater) N-type impurities per cubic centimeter. During theemitterditfusion the mask the silicon dioxide layer 20 selectively sothat a dotshaped and a pair of concentric ring-shaped portions coveringthe emitter, base and collector regions, respectively,

can be etched away. After etching away appropriate portions of thesilicon dioxide, contacting metals are evaporated into the dotandring-shaped etched-away portions and subsequently alloyed to thesemiconductor wafer to form electrical contacts thereto For example,aluminum has excellent electrical characteristics and, therefore, isdesirable contacting metal. However, since aluminum is a P-type dope insilicon, special precautions must be ,taken when alloying aluminum to.-N-type conductivity silicon to prevent creating a rectifying junction.The semiconductor device as shown in FIGURE 1e is designed so thatactive regions of the device. An aluminum contact 21 in aluminum can beohmically alloyed to all three active regions. For example, to achievedesirable operating char-1 V acteristics the emitter region of an NPNtransistor is heavily doped to approximately 10 9 impurities per cubiccentimeter. Because of the high doping level of the emitter region 18,aluminum may be alloyed thereto with only a very Weak rectifyingjunction'resulting. The heavily doped N-type region 19 has even a higherimpurity concentration level than the emitter region 18. Thus, aluminummay be alloyed withthat region without fear: of forming a harmfulrectifying junction. Itis apparent'that aluminum can be alloyed to theP-type base region '14 without forming a rectifying junction. Thus, thetransistor shown in FIGURE la is fabricated in such a way that aluminummay be used to form ohmic contacts to all three the form of a dot isformed on the emitter region 18 in the dot-shaped portion which has beenremoved from'the oxide layer 20. Likewise a ring-shaped aluminum contact22 is formed on the base region 14 and a concentric ringshaped aluminumcontact23 is provided for the n+ region 19 of the collector region 10wherethe oxide layer 20 has been removed. Of course,.conductive. leadsmay be attached to the contacts 21, 22 and 23 by any suitable techniquesuch as a ball-bonding procedure and the device then encapsulated in anappropriate housing such as a header and can. V i

As shown in FIGURE 12, a portion of the silicon dioxide layer20;defining a ring covers the exposed edge of the junction between theemitter region 18 and the base re- I gion 14. Likewise, rin g-shapedportions of the silicon dione of the junctions between the heavily dopedN-type conductivity region 19 and the collector region 10. The silicondioxide layer 20 including the ring-shaped portions covering thejunctions permanently remains on the surface of the transistor toprotect the normally exposed active junctions of the device fromcontamination during the manufacturing process and also afterincorporation into a completed assembly.

The transistor as shown by the pictorial View in FIG- URE 1e has thefeature of the emitter, base and collector contacts being positioned onthe top surface of the active device so that the transistor may easilybe electrically isolated from the header. In contrast to previouslyavailable planar transistors, the device provided by the presentinvention may be mounted on a metal header by means of an electricallyinsulating preform or ceramic wafer. Prior transistors necessarily madeuse of the bottom side of the active device for the collector contact.The invention provides a method for forming a highly doped region in thetop portion of the collector so that contacting material such asaluminum'may be alloyed thereto without the danger of a rectifyingjunction being formed therebetween. The highly doped region formed inthe top portion of the collector region serves the additional purpose ofacting as a barrier to prevent electrical shorting of the collectorregion due to surface inversion.

With reference to FIGURES 2a through 2d, there is shown a PNPNcontrolled rectifier and method of fabrication thereof which is verysimilar to the procedure of FIGURES la to 12. More specifically, FIGURE2a illustrates an N-type silicon wafer 25 which has had an oxide layer26 deposited on the upper surface thereof. A circular hole 27 has beenetched or otherwise removed from the oxide layer 26 to expose a surfaceportion 28 of the wafer 25. Both sides of the wafer 25 have beensubjected to a vapor-solid diffusion process so that P-type impuritiesare diffused into the lower surface and the exposed portion 28 of theupper surface to form a pair of P-type regions 29 and 30. As shown inFIGURE 2b, the remaining oxide layer 26 is removed from the uppersurface of the Wafer 25 and continuous oxide layers 31 and 32 are formedon both upper and lower surfaces by a procedure as described above.Selected portions of the oxide layer 31 are then removed as shown inFIGURE 20 wherein it is seen that a circular hole 33 exposes a surfaceportion 34 of the diffused P-type region 30 and a peripheral cutawayregion 35 exposes a surface area of the N-type wafer 25, The oxide layer32 on the lower surface remains intact. After the selected portions ofthe oxide layer 31 have been removed, the device is subjected to avapor-solid diffusion process such that an N-type region 36 is formed inthe exposed area 34 of the P-type region 30 and at the same timeadditional donor impurities are diffused into the N- type wafer 25 atthe exposed area 35 to create an N+ region 37. The remainder of theoxide layer 31 is then removed along with the oxide layer 32 on thelower surface and a continuous oxide layer 38 is formed on the uppersurface as may be seen in FIGURE 2d. A small dot'shaped portion isremoved from the center of the oxide layer 38 over the N-type region 36so that an aluminum contact 39 may be evaporated onto the region 36.Likewise, a pair of concentric ring-shaped portions are removed from theoxide layer 38 over the P-type region 30 and the N+ region 37,respectively, so that a pair of aluminum contacts 40 and 41,respectively, may be evaporated on the surface thereof. An aluminumcontact 42 is formed on the lower surface of the wafer over the P-typeregion 29. Conductive leads may be attached to the contacts 39, 40, 41,and 42 by conventional techniques.

The procedure just described provides a PNPN switching device orcontrolled rectifier as illustrated in FIGURE 2d having four electricalcontacts, three of which are positioned on the top surface of thedevice. The controlled rectifier shown in FIGURE 2d has'the samefeatures and advantages over the prior art as does the NPN transistorshown in FIGURE 1e. In addition the present invention 6 provides amethod and means for fabricating a silicon controlled rectifier withelectrical contacts to all four active regions, Whereas previouslyavailable controlled rectifiers have had only three electrodes.

It is apparent to those familiar withv the operation of a semiconductorcontrolled rectifier that once the conduction of the device has reachedthe avalanche value or saturation point a relatively large reversecurrent or a relatively large backward bias on the gate is necessary torender the device nonconductive. The controlled rectifier in FIGURE 2dis provided with an additional control electrode that aids in renderingthe device nonconductive. For example, the contacts 39, and 42 may bereferred to as the first emitter, gate and second emitter respectivelyof the standard controlled rectifier. The present invention provides thecontact 41 to the collector region 25 or 37. Thus, a current can beproduced in the collector region 75 through the contact 41 thatultimately results in a current gain to render the device conductive ornonconductive.

The method of fabricating the controlled rectifier as shown in FIGURE 2dis the same as the method for fabricating the NPN silicon transistorshown in FIGURE 1e except that the P-type conductivity region 29 isformed during the same diffusion step that the P-type conductivityregion 30 is formed. The same diifusant, times and temperatures areapplicable in the instant case. In a manner similar to the layer 24) ofFIGURE 13, the oxide layer 38 of FIGURE 2d protects the junctionsbetween the active regions of the device.

The present invention is also applicable to the formation of a highlydoped N-type region in the top portion of the collector region of a mesatransistor. A mesa transistor with the emitter, base and collectorcontacts positioned on the top surface of the wafer may be fabricatedaccording to a procedure shown in FIGURES 3a through 3d, the method forfabricating the mesa transistor being similar to that used for makingthe planar type transistors.

As seen in FIG. 3a, a wafer of N-type silicon is subjected to avapor-solid diffusion process to form a P-type region 51 adjacent to thetop surface thereof. An oxide coating is then formed over the entireupper surface, and a selected portion of the oxide is removed by amasking and etching technique, leaving a circular portion 52 of theoxide over the center of the wafer. The top surface of the wafer is thensubjected to a mesa etch process in a manner well known in the artwhereby the portion of the silicon not protected by the oxide layer 52is etched away, leaving a mesa 53 and exposing the PN junction and asurface 54 of the N-type layer 50. The oxide layer 52 is removed bycleaning, and another oxide layer 55 is formed over the mesa 53 and thesurface 54, as seen in FIGURE 3c. A circular hole 56 is formed in theoxide layer 55 on the top of the mesa by masking and etching, while aring-shaped hole 57 is formed around the outside of the mesa concentrictherewith. The top surface is then subjected to a vapor-solid diffusionprocess whereby an N-type region 58 is formed in the region 51 throughthe hole 56, while at the same time donor impurities diffuse into thewafer 50 through the hole 57 to form an annular N+ region 59. The oxidelayer 55 may then be removed, another oxide layer 60 deposited over theentire surface as seen in FIGURE 3d to protect the junctions. Adotshaped portion of the oxide layer 60 over the N-type emitter region58 is removed by selective masking and etching while a pair ofconcentric ring-shaped portions of oxide are removed from over theP-type base region 58 and the N+ region 59. Aluminum contacts 61, 62 and63 are then evaporated onto the regions 58, 51 and 59, respectively,through the areas which have been removed from the oxide, providing theemitter, base and collector contacts of an NPN transistor. Lead wiresmay be ballbonded or otherwise attached to the contacts 61, 62 and 63,and the wafer may be mounted on a header and encapsulated to completethe assembly.

tions of the oxide coating To form a mesa-type PNPN device, the lowersurface of the device of FIGS. 3a-3d may be processed in a mannersimilar to the device of FIGS. 2a-2d.

Although the invention has been described with reference to specificexamples, it will become apparent to those skilled in the art thatmodifications and substitutions can be made Without departing from thescope of the present invention which is intended to be limited only bythe appended claims.

What is claimed is: r

1. A method of making a semiconductor device comprising the steps ofintroducing an excess of impurities of one conductivity type into aselected surface region of "a face of a wafer of semiconductor materialof the opposite conductivity-type, introducing an excess of impuritiesof said opposite conductivity-type into a portion of said wafer withinthe said surface region and into a petripheral area on said face of saidWafer, said peripheral area being spaced from and surrounding saidsurface region, and depositing a material which has a tendency to impartsaid one conductivity-type to said semi-conductor material onto smallareas of said face of said Wafer including portions of the surface ofsaid surface region and of the surface of said peripheral area.

2. A method of making a semiconductor device comprising the steps ofapplying an oxide coating to a surface of a wafer of oneconductivity-type semiconductor mate-' rial, selectivity removing saidoxide coating from a given area of said surface of'the Wafer, diffusingan impurity of the opposite conductivity determining type into saidwafer to form a diffused region underlying the area where said oxidecoating has been removed, applying another oxide coating to said surfaceof said wafer, again selectively removing spaced portions of the oxidecoating from said surface of the wafer, one of said spaced portionsoverlying said difiused region and the other being spaced from saiddifiused region, and difiusing an impurity of said one conductivitydetermining type into said wafer in the regions underlying said spacedportions.

7 3. A method of making a semiconductor device comprising the steps ofapplying an oxide coating to a surface of a wafer of N-typesemiconductor material, selectively removing said oxide coating from agiven area of said surface of the wafer, diffusing a P-type conductivityspaced portionsand a diffused N-type region of very high excess impurityconcentration underlying said other of said'spaced portions. V

4. A method of making an NPN transistor comprising the steps of applyingan oxide coating to a surface of an N-type silicon wafer, selectivelyremoving said oxide coating from a given area of said surface of thewafer, diffusing a P-type conductivity determining impurity materialinto said surface to form a P-type diffused region under lying saidgiven area, applying another oxide coating to said surface, selectivelyremoving a pair of spaced porfrom said surface, one of said spacedportions overlying said P-type diffused region and the other beingspaced from said difiused region, diffusing an N-type conductivitydetermining impurity material into said surface to form a first diffusedN-type region under- 8 lying said one spaced portion and a seconddifi'used'N-type region underlying said other spaced portion, saidsecond diffused N-type region having a very high excess impurityconcentration, applying a further oxide coating to said surface,selectively removing the oxide coating from small areas overlying eachof said P-type and said first and sec ond N-type diffused regions, andevaporating aluminum into said small areas Where said oxide coating hasbeen removed. 7

5. A method of making a semiconductor device comprising the steps ofapplying an oxide coating to the top surface of a wafer of N-typesilicon, selectively removing said oxide coating from a given area ofsaid top surface,

' difiusing a P-type conductivity determining impurity material into thetop'and bottom surfaces of said wafer to form a first P-type diffusedregion adjacent said top surface underlying said given area and a secondP-type region adjacent said bottom surface, applying an oxide coating tothe top and bottom surface of said wafer, selectively removing spacedportions of the oxide coating on said top surface of said wafer, one ofsaid spaced portions overlying said first P-type diffused region and theother being spaced from said first P-type diffused region, and diffusingan N-type conductivity determining impurity material into said topsurface of the wafer to form a diffused N-type region underlying saidone of said spaced portions and a diffused N-type region of very highexcess impurity concentration underlying said other of said spacedportions. r V

6; A method of making a semiconductor device comprising the steps ofdiffusing an impurity of one conductivity determining type into asurface of a wafer of semiconductor material of the oppositeconductivity-type to form a diffused surface layer, applying an oxidecoating to said surface, selectively removing the oxide coating from theperiphery of said surface leaving a given area of said oxide coatingintact, applying an etchant to said 7 surface to remove thesemiconductor material from said surface to a depth exceeding that ofsaid diffused surface layer in the area not covered by said oxidecoating to form a mesa, applying an oxide coating to said surface of thewafer including the sides and top of said mesa, selectively removing theoxide coating from a small area on the top of said mesa and from a smallperipheral area spaced from said mesa, difiusing an impurity of saidopposite conductivity determining type into said surface in the areaswhere the oxide coating has been removed to form a diffused regionwithin said difiused'surface layer on the top of said mesa and aperipheral diffused portion surrounding said mesa, applying anotheroxide coating to said surface including the sides and top of said mesa,

selectively removing the oxide coating from small areas overlying saiddiffused region and said diffused surface layer on the top of said mesaand from a narrow peripheral area overlying said peripheral diffusedportion spaced from said mesa, and depositing a material having a,tendency to impart said one conductivity-type to said semiconductormaterial in the areas where the oxide coating has been removed. 7

References Cited UNITED STATES PATENTS Stelmak 148-185 HYLAND BI ZOT,Primary Examiner. A

4. A METHOD OF MAKING AN NPN TRANSISTOR COMPRISING THE STEPS OF APPLYINGAN OXIDE COATING TO A SURFACE OF AN N-TYPE SILICON WAFER, SELECTIVELYREMOVING SAID OXIDE COATING FROM A GIVEN AREA OF SAID SURFACE OF THEWAFER, DIFFUSING A P-TYPE CONDUCTIVITY DETERMINING IMPURITY MATERIALINTO SAID SURFACE TO FORM A P-TYPE DIFFUSED REGION UNDERLYING SAID GIVENAREA, APPLYING ANOTHER OXIDE COATING TO SAID SURFACE, SELECTIVELYREMOVING A PAIR OF SPACED PORTIONS OF THE OXIDE COATING FROM SAIDSURFACE, ONE OF SAID SPACED PORTIONS OVERLYING SAID P-TYPE DIFFUSEDREGION AND THE OTHER BEING SPACED FROM SAID DIFFUSED REGION, DIFFUSINGAN N-TYPE CONDUCTIVITY DETERMINING IMPURITY MATERIAL INTO